
2003 Microchip Technology Inc.
Preliminary
DS40300C-page 59
PIC16F62X
10.0 VOLTAGE REFERENCE
MODULE
The Voltage Reference is a 16-tap resistor ladder
network that provides a selectable voltage reference.
The resistor ladder is segmented to provide two ranges
of V
REF values and has a power-down function to
conserve power when the reference is not being used.
The VRCON register controls the operation of the
10.1
Configuring the Voltage Reference
The Voltage Reference can output 16 distinct voltage
levels for each range.
The equations used to calculate the output of the
Voltage Reference are as follows:
if V
RR = 1: VREF = (VR<3:0>/24) x VDD
if V
RR = 0: VREF = (VDD x 1/4) + (VR<3:0>/32) x
V
DD
The setting time of the Voltage Reference must be
considered when changing the V
REF output
to configure the Voltage Reference for an output
voltage of 1.25V with V
DD = 5.0V.
REGISTER 10-1:
VRCON REGISTER (ADDRESS: 9Fh)
FIGURE 10-1:
VOLTAGE REFERENCE BLOCK DIAGRAM
R/W-0
U-0
R/W-0
VREN
VROE
VRR
—VR3
VR2
VR1
VR0
bit 7
bit 0
bit 7
V
REN: VREF Enable
1
= VREF circuit powered on
0
= VREF circuit powered down, no IDD drain
bit 6
V
ROE: VREF Output Enable
1
= VREF is output on RA2 pin
0
= V
REF is disconnected from RA2 pin
bit 5
V
RR: VREF Range selection
1
= Low Range
0
= High Range
bit 4
Unimplemented: Read as '0'
bit 3-0
V
R<3:0>: VREF value selection 0
≤ VR [3:0] ≤ 15
When V
RR = 1: VREF = (VR<3:0>/ 24) * VDD
When V
RR = 0: VREF = 1/4 * VDD + (VR<3:0>/ 32) * VDD
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
Note
Vrr
8R
Vr3
Vr0
(From VRCON<3:0>)
16-1 Analog Mux
8R
R
V
REN
Vref
16 Stages
V
DD
V
SS
V
SS